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投稿时间：2016-03-16
投稿时间：2016-03-16
中文摘要: 以时域有限差分法的二维形式为例，用Verilog HDL语言加以实现.采用32位单精度浮点数进行加减法和乘法运算，以保证计算的精度.通过modelsim软件仿真，以Altera FPGA的硬件实现来确保设计的正确性.实验结果显示，基于FPGA的时域有限差分法硬件实现方法对提高速度效果明显，是提高算法性能的有效途径.
中文关键词: 时域有限差分法 可编程逻辑器件 Verilog硬件描述语言 二维TM波
Abstract:Finite difference time Domain algorithm is a popular algorithm in the computation electromagnetic.However,the huge computing capacity is a limiting factor for its applications.This paper presents implementation of the 2D FDTD algorithm by FPGA whose circuit is described by the verilog HDL.32 Bit single-precision floating-point specification is adopted to ensure the accuracy of calculation.After the Modelsim software simulation,the correctness of the design is ensured by the hardware implementation of Altera FPGA.The experimental results show that FPGA implementation speeds up the algorithm greatly.Thus,it becomes an effective way to improve the performance of FDTD algorithm.
文章编号：20171015 中图分类号： 文献标志码：
基金项目:
| 作者 | 单位 | |
| 赵倩 | 上海电力学院 电子与信息工程学院 | zhaoqian@shiep.edu.cn |
| Author Name | Affiliation | |
| ZHAO Qian | School of Electronics and Information Engineering, Shanghai University of Electric Power, Shanghai 200090, China | zhaoqian@shiep.edu.cn |
引用文本：
赵倩.基于FPGA时域有限差分算法的设计与实现[J].上海电力大学学报,2017,33(1):69-72,96.
ZHAO Qian.An FPGA Implementation of Finite Difference Time Domain Algorithm[J].Journal of Shanghai University of Electric Power,2017,33(1):69-72,96.
赵倩.基于FPGA时域有限差分算法的设计与实现[J].上海电力大学学报,2017,33(1):69-72,96.
ZHAO Qian.An FPGA Implementation of Finite Difference Time Domain Algorithm[J].Journal of Shanghai University of Electric Power,2017,33(1):69-72,96.