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投稿时间：2005-04-19
投稿时间：2005-04-19
中文摘要: 用(σ,ρ,λ)调节器取代(σ,ρ)调节器,在齐次网络中,讨论了当进入网络的信息包的最大长度L>0和信息流的速率函数R(t)∈{0,C}时,任一比特在单个调节转换器中的延迟.证明了存在一个最优值(也是最小值)ρ*,当信息流平均速率ρ≥ρ*时,任一比特之最大延迟比未调节时要小;而当ρ<ρ*时,最大延迟比未调节时要大.
Abstract:Substiting the(σ,ρ,λ)regulator for the(σ,ρ) regulator in the homogeneous system,we research the delay of any data bit(supposing L>0,R(t)∈{0,C),where L is the biggest length of the packet,R(t)is the rate function of traffic flows entering a network)in a single regulated multiplexer(including general MUX and LFCFS MUX).It is shown that there exists an optimal(i.e.,minimum) ρ* such that Dr≥D for ρ*>ρ and Dr≤D for ρ≥ρ*,where Dr and D are the worst-case delay bounds regulated by(σ,ρ,λ)regulator and not regulated by(σ,ρ)regulator respectively.
文章编号：20050316 中图分类号： 文献标志码：
基金项目:
| 作者 | 单位 |
| 于娜 | 上海电力学院 数理系, 上海 200090 |
| Author Name | Affiliation |
| YU Na | Dept. of Mathematics and Physics, Shanghai University of Electric Power, Shanghai 200090, China |
引用文本：
于娜.单个调节转换器中高速实时信息流的延迟保证[J].上海电力大学学报,2005,21(3):261-267.
YU Na.Delay Guarantee for Real-time Traffic Flows with High Rate in a Single Regulated Multiplexer[J].Journal of Shanghai University of Electric Power,2005,21(3):261-267.
于娜.单个调节转换器中高速实时信息流的延迟保证[J].上海电力大学学报,2005,21(3):261-267.
YU Na.Delay Guarantee for Real-time Traffic Flows with High Rate in a Single Regulated Multiplexer[J].Journal of Shanghai University of Electric Power,2005,21(3):261-267.